
-- VHDL Instantiation Created from source file rgb.vhd -- 20:36:15 03/13/2014
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT rgb
	PORT(
		clk_in : IN std_logic;
		empty : IN std_logic;
		pixel_data : IN std_logic_vector(7 downto 0);          
		ready : OUT std_logic;
		red_out : OUT std_logic_vector(7 downto 0);
		green_out : OUT std_logic_vector(7 downto 0);
		blue_out : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	Inst_rgb: rgb PORT MAP(
		clk_in => ,
		empty => ,
		pixel_data => ,
		ready => ,
		red_out => ,
		green_out => ,
		blue_out => 
	);


